1. Field of the Invention
The present invention relates to a scanning line driving circuit, and more particularly to a scanning line driving circuit for use as, e.g., an electro-optic apparatus such as an image display apparatus and an image sensor and constituted by only field-effect transistors of the same conductivity type.
2. Description of the Background Art
In an image display apparatus (hereinafter referred to as a “display apparatus”) such as a liquid crystal display apparatus, a plurality of pixels are arranged in a matrix on a display panel, and a gate line (scanning line) is provided for each row of pixels (pixel line) of the display panel. In a cycle of one horizontal period of a display signal, the gate lines are sequentially selected and driven to update a display image. As a gate line driving circuit (scanning line driving circuit) for sequentially selecting and driving pixel lines, i.e., gate lines, a shift register may be used, which performs a round of shift operation in one frame period of a display signal.
In order to reduce the number of steps in the manufacturing process of a display apparatus, a shift register for use as a gate line driving circuit should preferably be constituted by only field-effect transistors of the same conductivity type. Therefore, various types of shift registers constituted by only N- or P-type field-effect transistors, and various display apparatuses containing such shift registers have been proposed (e.g., in Japanese Patent Application Laid-open No. 2004-78172).
A shift register for use as a gate line driving circuit is constituted by a plurality of cascade-connected shift register circuits, each of which is provided for each pixel line, i.e., each gate line. In this specification, for convenience of description, each of a plurality of shift register circuits forming a gate line driving circuit is referred to as a “unit shift register.” In other words, an output terminal of each unit shift register constituting a gate line driving circuit is connected to an input terminal of a unit shift register of a subsequent stage or a later stage.
FIG. 7 of Japanese Patent Application Laid-open No. 2004-78172 illustrates a configuration of a conventional unit shift register. As shown in FIG. 7 thereof, the conventional unit shift register includes a first transistor (M1) connected between an output terminal (GOUT[N]) and a clock terminal (CKV) and a second transistor (M2) connected between the output terminal and a first power supply terminal (VOFF). The unit shift register outputs an output signal, when a clock signal input to the clock terminal is transmitted to the output terminal while the first transistor is on and the second transistor is off.
In particular, it is necessary for a gate line driving circuit to activate a gate line by charging it rapidly using the output signal, and accordingly, in each unit shift register constituting the gate line driving circuit, the first transistor is required to have a high drive capability (a capability to pass current). Therefore, while the first transistor is on, it is desirable to keep a voltage between the gate and the source at a high state.
A first node (N1), to which the gate of the first transistor is connected, is connected to a third transistor (M3) for charging the first node. In the conventional unit shift register, the third transistor is connected between the first node and a second power supply terminal (VON), and the gate of the third transistor is connected to an input terminal of the corresponding unit shift register (i.e., an output terminal (GOUT[N−1]) of a unit shift register of a preceding stage). In other words, the third transistor turns on when an output signal of the unit shift register of the preceding stage is activated, and charge is provided to the first node from a power supply connected to the second power supply terminal so as to charge the first node (pre-charge). Thereby, the first transistor turns on, and thereafter, when the clock signal attains a high (H) level, it is transmitted to the output terminal, and an output signal is output.
The shift register circuit of Japanese Patent Application Laid-open No. 2004-78172 is arranged with a capacitor element (C) between the first node and the output terminal, i.e., the source of the first transistor. Therefore, when the pre-charge of the first node causes the first transistor to turn on, and thereafter the output terminal attains the H level in accordance with the clock signal, the potential at the first node increases with the coupling via the capacitor element, so that the voltage between the gate and source of the first transistor is kept high. As a result, the first transistor has a high drive capability.
However, while the potential at the first node is being increased, the voltage between the gate and source of the first transistor does not increase compared with the state before the potential is increased, and it is merely kept about the same. In other words, the drive capability of the first transistor in the unit shift register is determined based on the voltage between the gate and source which is given during the pre-charge performed by the third transistor. Therefore, in order to increase the drive capability of the first transistor, it is necessary to charge the first node to a sufficiently high level during the pre-charge.
Where the H level of the clock signal and the potential at the second power supply terminal are VDD, and a threshold voltage of the third transistor is Vth, the potential at the first node can be theoretically increased to VDD−Vth by the pre-charge. However, when the frequency of the clock signal increases, and a pulse width of the input signal (the output signal of the unit shift register of the preceding stage) becomes narrow, it is difficult for the first node to attain the maximum pre-charge level (VDD−Vth). One of the reasons therefore is that the third transistor (M3) operates in a source-follower mode during the pre-charge of the first node. In other words, this is because, when the level of the first node increases, the voltage between the gate and source of the third transistor decreases, and therefore, the drive capability of the third transistor decreases in accordance with the progress of charging of the first node, so that the rising rate of the level greatly decreases.
In other words, in the conventional unit shift register, the gate of the first transistor (the first node) is pre-charged by the third transistor operating in the source-follower mode, and therefore, it takes a relatively long time to charge the first node to the maximum pre-charge level. Therefore, when the frequency of the clock signal increases, the first node cannot be sufficiently pre-charged, which brings about a decrease in the drive capability of the first transistor. In particular, the gate line driving circuit has a problem in that it is necessary to activate a gate line by charging it rapidly using the output signal of the unit shift register, thus requiring the first transistor to have a high drive capability. In other words, there is a problem in that it is difficult to cause the gate line driving circuit to operate faster by increasing the frequency of the clock signal, which hinders a display apparatus from achieving a high resolution.